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DIY For Audio
Forum DAC tweaking thread
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<blockquote data-quote="DACMan1" data-source="post: 23462" data-attributes="member: 112"><p>There is a guy somewhere on the net that did the ram buffer thing. Used a CPLD. I am trying to find time to do something similar, but this would be a significant exercise, in both hardware and firmware. The most cost effective device would be a Xilinx spartan 3. Development boards can be had for R500. Then you just need to add an external board with SRAM and DACs. SPDIF can be decoded in the FPGA, but it might be worthwhile just to use an external DIR9001 or the chip you used. The great part, however is that you can do digital filtering on the FPGA and implement minimal phase or linear phase FIR filters. This means that you can make an active system (one DAC channel per driver) that uses all digital FIR filters... We are currently investigating if we could fit a stereo 3-way FIR into the device on the demoboard.</p></blockquote><p></p>
[QUOTE="DACMan1, post: 23462, member: 112"] There is a guy somewhere on the net that did the ram buffer thing. Used a CPLD. I am trying to find time to do something similar, but this would be a significant exercise, in both hardware and firmware. The most cost effective device would be a Xilinx spartan 3. Development boards can be had for R500. Then you just need to add an external board with SRAM and DACs. SPDIF can be decoded in the FPGA, but it might be worthwhile just to use an external DIR9001 or the chip you used. The great part, however is that you can do digital filtering on the FPGA and implement minimal phase or linear phase FIR filters. This means that you can make an active system (one DAC channel per driver) that uses all digital FIR filters... We are currently investigating if we could fit a stereo 3-way FIR into the device on the demoboard. [/QUOTE]
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DIY For Audio
Forum DAC tweaking thread
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